1. Field of the Invention
The invention relates generally to superscalar processors and, more particularly, relates to processor systems capable of executing a plurality of instructions in a parallel manner with a plurality of processing units provided in parallel.
2. Description of the Background Art
A superscalar processor is a high-performance microprocessor having a parallel processing mechanism called "superscalar type" built therein and described, for example, in S. McGeady "The i960CA Superscalar Implementation of the 80960 Architecture", COMPCON 1990 IEEE pp. 232-240 or Randy D. Groves "An IBM Second Generation RISC Processor Architecture", COMPCOM 1990 IEEE pp. 166-172. In the superscalar type, a plurality of processing units provided in parallel execute a plurality of instructions in a parallel manner. The superscalar processor simultaneously fetches a plurality of instructions from an instruction memory and decodes the same. It selects instructions which can be processed in a parallel manner from the decoded instructions and supplies the same to the processing units.
A superscalar processor as stated above is expected to be applied for a variety of purposes since the performance of processing can be remarkably enhanced compared with that of a conventional normal microprocessor.
FIG. 4 shows a general structure of a conventional superscalar processor. In the figure, a plurality of instructions to be processed are stored in an instruction memory 1. An instruction fetch circuit 2 reads out a plurality of instructions (for example, four instructions) from instruction memory 1 at the same time and fetches the same. An instruction decoder 3 decodes the plurality of instructions fetched by instruction fetch circuit 2, selects instructions which can be processed in a parallel manner and supplies the same to processing units 4 to 7. Processing units 4 to 7 have a pipeline structure, for example, and each of them independently executes a supplied instruction. Though the contents to be processed in processing units 4 to 7 may be undetermined, processing units 4 and 5 are structured as integer arithmetic units in FIG. 4, processing unit 6 is structured as a unit for loading or storing to a data memory 8, and processing unit 7 is structured as a floating-point arithmetic unit. Data memory 8 is a memory for storing data.
As stated above, since the superscalar processor shown in FIG. 4 can simultaneously execute a plurality of instructions in a parallel manner, a processing speed can be increased compared with that of a normal microprocessor.
The superscalar processor shown in FIG. 4 operates for each cycle of a clock signal (not shown) synchronizing with the clock signal. FIG. 5 is a diagram showing one example of instruction fetch and instruction output of the superscalar processor of FIG. 4 in four successive cycles. A description will be made below of one example of the operation of the superscalar processor shown in FIG. 4 with reference to FIG. 5.